The present invention relates to a vertical power semiconductor device (hereinafter referred to as “power device”) primarily made of silicon carbide (SiC) semiconductor material and capable of voltage driving through an insulated gate.
Devices that handle a large amount of electric power, so-called power devices, have been conventionally manufactured by primarily using silicon semiconductors. Since a power device can have a large electric current capacity, it often has a structure in which electric current flows in the thickness direction (vertical direction) between the two principal planes of the chip. Among such conventional power devices, FIG. 9 is a cross-sectional view of a conventional representative vertical insulated gate field effect transistor (MOSFET).
The cross-sectional view of a semiconductor substrate shown in FIG. 8 is the basic structure of a well known device called a static induction transistor (hereinafter abbreviated as “SIT”). This structure includes gates obtained by selectively burying p+ regions 4 in an n-type high-resistance drift layer 3 deposited on an n+ semiconductor substrate 1. When a negative bias with respect to a drain 6 provided on the underside of the semiconductor substrate 1 is applied to the gate, a depletion layer expands in a pinch-off region 9 provided between each pair of the p+ regions 4, which are the gates, and blocks the electric current path from the drain 6 through the pinch-off region 9 and an n+ source region 7 to a source 8. Such a SIT devices are characterized by a monopolar structure in which electric current basically only flows through n-type regions, so that small on-resistance close to an ideal value is likely provided. Prototype devices have been reported having the SIT structure using SiC semiconductors with excellent characteristics as well as those using silicon semiconductors. In the basic structure of the SIT device, however, each of the gates 4 is formed by means of a pn junction. Therefore, when the junction gets degraded or the gate circuit malfunctions, the gate bias becomes defective, so that the device remains conducting, possibly resulting in a serious failure, such as breakdown of the circuit in the worst case. Accordingly, use of the SIT device requires caution in the gate bias conditions, which poses difficulty in using the SIT device.
The vertical MOSFET, an insulated gate device, is frequently used as the power device described above, and is shown in the cross-sectional view of FIG. 9. FIG. 9 shows a typical planar gate MOSFET in which gate insulating films 24 and gate electrodes 23, each having a flat shape, are formed on the principal plane of a semiconductor substrate (20+22a). N+ regions 28 and a p+ region 26 that is provided to make ohmic contact are provided in a p-well 25. In FIG. 9, n+ surface regions 22b that are provided immediately under the gate insulating films 24 and located outside the p-well 25 in the substrate surface are not formed in many cases. When reduction in size of the unit pattern for lowering on-resistance narrows the n-type region immediately under the gate sandwiched between the p-wells 25 in adjacent unit patterns, the pinch-off resistance increases because a depletion layer expands when a bias is applied to a drain 29. To prevent the pinch-off resistance and hence the on-resistance from increasing, the high-concentration n+ surface regions 22b are provided. The concentration (impurity concentration) is approximately 1×1018 cm−3 at the most, because higher concentrations prevent the depletion layer from expanding along the surface, resulting in reduction in blocking voltage. Reference numeral 30a denotes an interlayer insulating film, and reference numeral 27 denotes a source.
In the vertical MOSFET, unlike the SIT, the on-resistance of the element includes not only the resistance of the n-type semiconductor region (the high-resistance drift region, in particular) but also the channel resistance in the MOSFET portion. On the other hand, the total resistance of the channel regions in the whole element decreases when the size of the unit pattern is reduced to increase the channel density, since the channels are connected in parallel in terms of an equivalent circuit. Accordingly, to lower the on-resistance of the whole element, the unit pattern is preferably formed in such a way that the channel density increases.
The cross-sectional view of FIG. 10 shows a conventional trench gate MOSFET devised in such a way that more reduction in channel resistance through the size reduction is achieved. The same reference characters shown in FIG. 10 as those in FIG. 9 indicate the regions having similar functions. In the device illustrated in FIG. 10, the impurity concentration of an n buffer layer 21 is higher than an impurity concentration of a n− region 22a and is lower than an impurity concentration of an n+ semiconductor substrate 20. In the MOS gate structure indicated by the reference numerals 23, 24, and 10 in FIG. 10, a trench 10 extends downward perpendicularly to the principal plane in such a way that the trench 10 extends through the p-well 25 and reaches the n region 22a, so that the trench density along the surface can be easily enhanced. The MOS gate structure (23, 24, and 10) therefore easily achieves a higher channel density than that in the planar gate structure shown in FIG. 9. Furthermore, in this structure, the fact that no n-type region sandwiched between the p-wells structurally lowers the pinch-off resistance makes the trench gate MOSFET more advantageous than the planar gate MOSFET from the viewpoint of the pinch-off resistance.
However, in a silicon power device, since the channel density has been maximized by making full use of the fabrication technology of the trench gate structure and the LSI microprocessing technology, the characteristics of the silicon power device have approached the limit determined by the material. To break through this material limit, there have been attempts to change the semiconductor material from silicon to any of those having broader band gaps, such as SiC and GaN. Since the maximum breakdown fields of these materials are larger by approximately one order of magnitude than that of silicon, it is expected that use of any of these materials for a power device lowers the resistance of the element to one hundredth or smaller. Prototypes of SiC-MOSFET devices and SiC-SIT devices having structures similar to those of silicon devices have been built and have shown excellent characteristics.
For example, JP-A-2006-147789 filed by Yatsuo et al. (corresponding to International Patent Application WO 2006/054394 A1, and corresponding to European Patent Application EP 1,814,162 A1) describes an SiC-MOSFET in which the on-resistance is lowered by forming a structure including an n+ SiC substrate, an n-type drift layer stacked thereon, a high-concentration p-gate layer buried therein, and a MOS channel region further formed thereon, the MOS channel region being a low-concentration p-type deposition layer. It is necessary to selectively convert the p-type deposition layer into an n-type base region through ion implantation to form an electric current path. However, the n-type base region cannot be thick due to the practical limit of depth to which ions can be implanted (equal to the thickness of the p-type deposition layer), so that a high electric field is applied to the gate insulating film and hence the off-state voltage cannot be improved. To solve this problem, Yatsuo et al. report interposing a low-concentration n-type deposition layer between the low-concentration p-type deposition film and the high-concentration gate layer of a SiC MOSFET. The base region converted into the n-type through ion implantation is selectively formed in the low-concentration p-type deposition film so as to increase the thickness of the n-type deposition film between the high-concentration gate layer and the low-concentration p-type deposition film (channel region).
As described above, a MOSFET made of silicon carbide semiconductor is expected to have excellent characteristics because its dielectric breakdown field is higher than that of a silicon semiconductor by one order of magnitude. In practice, however, problems result from the fact that SiO2 film is primarily used as the gate insulating film as in a silicon semiconductor. For example, particularly in a trench MOSFET, the electric field concentrates at the corners of the gate insulating film, so that an excessive electric field is applied. An electric field normally applied in SiC cannot therefore be applied, so that only a much lower blocking voltage is provided. Accordingly, to avoid the problem of reduced blocking voltage due to dielectric breakdown of the gate insulating film in SiC, a planar gate MOSFET has been fabricated as a prototype in many cases.
Since a SiC semiconductor has lower channel mobility in a MOSFET than a silicon semiconductor, it is desirable to maximize the channel density so as to lower the channel resistance. However, in a planar gate MOSFET, which suffers from a low level of channel size reduction as described above, a sufficiently high channel density is not always provided. Since an SIT uses no gate insulating film, it does not have the problem described above. However, a SiC-SIT is a so-called normally-on device as in a silicon device, that is, it has source-drain continuity in the no-bias state in which no voltage is applied to the gate. This becomes a problem when a SiC-SIT is actually applied to a circuit, and hence a SiC-SIT is regarded as a hard-to-use device. For example, when a trouble occurs and destroys the gate circuit and no voltage can be applied to the gate, a so-called normally-off device is preferable from the viewpoint of safety because a normally-off power device blocks electric current.
As a method to eliminate the normally-on device function from a power device, there has been proposed a device structure shown in an equivalent circuit in FIG. 7. This device has a structure in which a SIT 18 and a MOSFET 17, which is a low blocking voltage normally-off device, are cascoded. When an off-state signal is applied to the gate 15, the MOSFET 17 becomes blocked, so that the potential at the source region of the SIT 18 increases. A negative bias is therefore applied to the gate of the SIT, so that the SIT 18 is also turned off. This configuration, however, results in a device in which the MOSFET 17 is added to the SIT 18, which means that the advantage of a SiC semiconductor device, small on-resistance with a small area, is lost.
In view of the above, it would be preferable to provide an insulated gate silicon carbide semiconductor device and a method for manufacturing the same, wherein the semiconductor device has a small on-resistance, the advantage of the static induction transistor structure is fully used, and the advantage of the insulated gate field effect transistor structure characterized by the normally-off operation is obtained, in a structure obtained by combining the static induction transistor structure with the insulated gate field effect transistor structure.